A high-level synthesis methodology for low-power VLSI design
- 17 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 9 references indexed in Scilit:
- Microarchitectural synthesis of performance-constrained, low-power VLSI designsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Power dissipation of VLSI array processing systemsJournal of Signal Processing Systems, 1992
- HYPER-LP: a system for power minimization using architectural transformationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1992
- Force-directed scheduling for the behavioral synthesis of ASICsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1989
- Optimizing Synchronous Circuitry by Retiming (Preliminary Version)Published by Springer Nature ,1983
- Algorithm 97: Shortest pathCommunications of the ACM, 1962
- Critical-Path Planning and Scheduling: Mathematical BasisOperations Research, 1961
- A Network Flow Computation for Project Cost CurvesManagement Science, 1961
- Maximal Flow Through a NetworkCanadian Journal of Mathematics, 1956