A testable realization of CMOS combinational circuits
- 13 January 2003
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 509-518
- https://doi.org/10.1109/test.1989.82334
Abstract
No abstract availableKeywords
This publication has 14 references indexed in Scilit:
- On the design of robust testable CMOS combinational logic circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Built-in self-test of a CMOS ALUIEEE Design & Test of Computers, 1988
- Fault Detection and Design For Testability of CMOS Logic CircuitsPublished by Springer Nature ,1988
- Designing CMOS Circuits for Switch-Level TestabilityIEEE Design & Test of Computers, 1987
- Graph-Based Algorithms for Boolean Function ManipulationIEEE Transactions on Computers, 1986
- Testable Realizations for FET Stuck-Open Faults in CMOS Combinational Logic CircuitsIEEE Transactions on Computers, 1986
- Design of Testable CMOS Logic Circuits Under Arbitrary DelaysIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1985
- Binary Decision DiagramsIEEE Transactions on Computers, 1978
- Representation of Switching Circuits by Binary-Decision ProgramsBell System Technical Journal, 1959
- The Synthesis of Two-Terminal Switching CircuitsBell System Technical Journal, 1949