Soft-error-rate improvement in advanced BiCMOS SRAMs
- 1 January 1993
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 26, 156-160
- https://doi.org/10.1109/relphy.1993.283330
Abstract
An improvement in soft-error-rate (SER) achieved by implementing a triple-well structure in a BiCMOS process is discussed. For 4-Mb SRAMs fabricated in a BiCMOS process, an optimized triple-well process improves the accelerated SER (ASER) by over two orders of magnitude without compromising device performance. Diode charge collection and ASER measurements show excellent correlation across several BiCMOS and CMOS processes.Keywords
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