A 60 MBd, 480 Mb/s, 256 QAM decision-feedback equalizer in 1.2 mu m CMOS

This publication has 10 references indexed in Scilit:

• Wave digital filters using carry-save arithmetic
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• High-speed architectures for algorithms with quantizer loops
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• CMOS digital adaptive decision feedback equalizer chip for multilevel QAM digital radio modems
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• An 85-MHz fourth-order programmable IIR digital filter chip
  IEEE Journal of Solid-State Circuits, 1992
• A 200-MHz all-digital QAM modulator and demodulator in 1.2- mu m CMOS for digital radio applications
  IEEE Journal of Solid-State Circuits, 1991
• A reconfigurable decision-feedback equalizer chip set architecture for high bit-rate QAM digital modems
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,1991
• High-speed CMOS circuit technique
  IEEE Journal of Solid-State Circuits, 1989
• A 6.75 ns 16*16 bit multiplier in single-level-metal CMOS technology
  IEEE Journal of Solid-State Circuits, 1989
• A roundoff error analysis of the LMS adaptive algorithm
  IEEE Transactions on Acoustics, Speech, and Signal Processing, 1984
• A CMOS floating point multiplier
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,1984