Defect-controlled generation in deeply depleted MOS-C structures
- 1 August 1975
- journal article
- research article
- Published by AIP Publishing in Applied Physics Letters
- Vol. 27 (3) , 148-150
- https://doi.org/10.1063/1.88388
Abstract
A model and supporting experimental evidence are presented to explain the nonlinear carrier generation rate versus semiconductor depletion width dependence which is frequently observed in the course of carrier generation lifetime (τ0) measurements. Experimental observations indicate a direct correlation between the occurrence of the nonlinear generation rate exhibited by MOS‐C structures and a large Si defect concentration, thereby suggesting that, when the defect concentration is large, the carrier generation rate within a structure is totally dominated by enhanced generation from bulk centers positioned in the vicinity of defect sites.This publication has 9 references indexed in Scilit:
- Field-enhanced carrier generation in MOS capacitorsSolid-State Electronics, 1974
- Oxidation-induced stacking faults in silicon. I. Nucleation phenomenonJournal of Applied Physics, 1974
- Oxidation-induced stacking faults in silicon. II. Electrical effects in P N diodesJournal of Applied Physics, 1974
- The Effect of Silicon Wafer Imperfections on Minority Carrier Generation and Dielectric Breakdown in MOS StructuresJournal of the Electrochemical Society, 1974
- An experimental determination of the carrier lifetime near the SiSiO2 interfaceSolid-State Electronics, 1973
- A linear-sweep MOS-C technique for determining minority carrier lifetimesIEEE Transactions on Electron Devices, 1972
- Interpretation of surface and bulk effects using the pulsed MIS capacitorSolid-State Electronics, 1971
- Surface effects on p-n junctions: Characteristics of surface space-charge regions under non-equilibrium conditionsSolid-State Electronics, 1966
- Carrier Generation and Recombination in P-N Junctions and P-N Junction CharacteristicsProceedings of the IRE, 1957