Modeling of hole confinement gate voltage range for SiGe channel p-MOSFETs
- 31 January 1996
- journal article
- Published by Elsevier in Solid-State Electronics
- Vol. 39 (1) , 69-73
- https://doi.org/10.1016/0038-1101(95)00101-x
Abstract
No abstract availableKeywords
This publication has 9 references indexed in Scilit:
- Inversion charge modeling of SiGe PMOS and approaches to increasing the hole density in the SiGe channelSolid-State Electronics, 1995
- SiGe-channel heterojunction p-MOSFET'sIEEE Transactions on Electron Devices, 1994
- High-mobility GeSi PMOS on SIMOXIEEE Electron Device Letters, 1993
- Hole mobility enhancement in MOS-gated Ge/sub x/Si/sub 1-x//Si heterostructure inversion layersIEEE Electron Device Letters, 1992
- High-mobility modulation-doped SiGe-channel p-MOSFETsIEEE Electron Device Letters, 1991
- A gate-quality dielectric system for SiGe metal-oxide-semiconductor devicesIEEE Electron Device Letters, 1991
- Hole confinement MOS-gated Ge/sub x/Si/sub 1-x//Si heterostructuresIEEE Electron Device Letters, 1991
- Enhancement-mode quantum-well Ge/sub x/Si/sub 1-x /PMOSIEEE Electron Device Letters, 1991
- Calculation of critical layer thickness versus lattice mismatch for GexSi1−x/Si strained-layer heterostructuresApplied Physics Letters, 1985