Performance optimization of pipelined logic circuits using peripheral retiming and resynthesis
- 1 May 1993
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 12 (5) , 568-578
- https://doi.org/10.1109/43.277605
Abstract
No abstract availableThis publication has 8 references indexed in Scilit:
- Logic decomposition algorithms for the timing optimization of multi-level logicPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Timing optimization of combinational logicPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Retiming synchronous circuitryAlgorithmica, 1991
- Synchronous logic synthesis: algorithms for cycle-time minimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1991
- Retiming and resynthesis: optimizing sequential networks with combinational techniquesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1991
- Timing optimization of multiphase sequential logicIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1991
- Performance-Oriented Synthesis of Large-Scale Domino CMOS CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- Optimizing synchronous systemsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1981