A 10 MHz (255, 223) Reed-Solomon decoder

Publisher Website

6 January 2003

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

https://doi.org/10.1109/cicc.1988.20889

Abstract

No abstract available

Keywords

This publication has 5 references indexed in Scilit:

A VLSI Design of a Pipeline Reed-Solomon Decoder
IEEE Transactions on Computers, 1985
Algebraic fields, signal processing, and error control
Proceedings of the IEEE, 1985
Systolic VLSI Arrays for Polynomial GCD Computation
IEEE Transactions on Computers, 1984
Architecture for VLSI Design of Reed-Solomon Decoders
IEEE Transactions on Computers, 1984
Why systolic architectures?
Computer, 1982