Expected value analysis of combinational logic networks

This publication has 12 references indexed in Scilit:

• Verification of timing constraints on large digital systems
  Published by Association for Computing Machinery (ACM) ,1988
• Probabilistic Treatment of General Combinational Networks
  IEEE Transactions on Computers, 1975
• The Probability of a Correct Output from a Combinational Circuit
  IEEE Transactions on Computers, 1975
• LAMP: Logic-Circuit Simulators
  Bell System Technical Journal, 1974
• TEGAS2---anatomy of a general purpose TEST GENERATION AND SIMULATION system for digital logic
  Published by Association for Computing Machinery (ACM) ,1972
• A Statistical Approach to the Computation of Delays in Logic Circuits
  IEEE Transactions on Computers, 1969
• A three-value computer design verification system
  IBM Systems Journal, 1969
• Pert as an Aid to Logic Design
  IBM Journal of Research and Development, 1966
• Mathematical Models for Predicting Pulse Characteristics in Digital Logic Systems
  IEEE Transactions on Electronic Computers, 1964
• Statistical Analysis of Logic Circuit Performance in Digital Systems
  Proceedings of the IRE, 1961