The origins of the performance degradation of implanted p/sup +/ polysilicon gated p-channel MOSFET with/without rapid thermal annealing

This publication has 13 references indexed in Scilit:

• Constraints in p-channel device engineering for submicron CMOS technologies
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• The use of ultrathin reoxidized nitrided gate oxide for suppression of boron penetration in BF/sub 2//sup +/-implanted polysilicon gated p-MOSFETs
  IEEE Electron Device Letters, 1991
• A comprehensive study on p/sup +/ polysilicon-gate MOSFET's instability with fluorine incorporation
  IEEE Transactions on Electron Devices, 1990
• Anomalous C-V characteristics of implanted poly MOS structure in n/sup +//p/sup +/ dual-gate CMOS technology
  IEEE Electron Device Letters, 1989
• Interface trap-enhanced gate-induced leakage current in MOSFET
  IEEE Electron Device Letters, 1989
• Stress voltage polarity dependence of thermally grown thin gate oxide wearout
  IEEE Transactions on Electron Devices, 1988
• Subbreakdown drain leakage current in MOSFET
  IEEE Electron Device Letters, 1987
• The impact of gate-induced drain leakage current on MOSFET scaling
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,1987
• Polysilicon capacitor failure during rapid thermal processing
  IEEE Transactions on Electron Devices, 1986
• Electrical Breakdown in Thin Gate and Tunneling Oxides
  IEEE Journal of Solid-State Circuits, 1985