A sub-10-ns 16×16 multiplier using 0.6-μm CMOS technology
- 1 October 1987
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 22 (5) , 762-767
- https://doi.org/10.1109/jssc.1987.1052811
Abstract
No abstract availableKeywords
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