A dual mode IEEE multiplier
- 22 November 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableThis publication has 4 references indexed in Scilit:
- Rounding algorithms for IEEE multipliersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A 17 × 69 bit multiply and add unit with redundant binary feedback and single cycle latencyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- 167 MHz radix-4 floating point multiplierPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- VLSI floating-point processorsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1985