167 MHz radix-4 floating point multiplier
- 19 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 20, 149-154
- https://doi.org/10.1109/arith.1995.465364
Abstract
An IEEE floating point multiplier with partial support for subnormal operands and results is presented. Radix-4 or modified Booth encoding and a binary tree of 4:2 compressors are used to generate the 53/spl times/53 double-precision product. Delay matching techniques were used in the binary tree stage and in the final addition stage to reduce cycle time. New techniques in rounding and sticky-bit generation were also used to reduce area and timing. The overall multiplier has a latency of 3 cycles a throughput of 1 cycle, and a cycle time of 6.0 ns. This multiplier has been implemented in a 0.5 /spl mu/m static CMOS technology in the UltraSPARC RISC microprocessor.Keywords
This publication has 9 references indexed in Scilit:
- Rounding algorithms for IEEE multipliersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- High-speed multiplier design using multi-input counter and compressor circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A Pipelined 64x64b Iterative Array MultiplierPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1988
- On the implementation of shifters, multipliers, and dividers in VLSI floating point unitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1987
- Balanced delay trees and combinatorial division in VLSIIEEE Journal of Solid-State Circuits, 1986
- A Proof of the Modified Booth's Algorithm for MultiplicationIEEE Transactions on Computers, 1975
- A Suggestion for a Fast MultiplierIEEE Transactions on Electronic Computers, 1964
- Conditional-Sum Addition LogicIEEE Transactions on Electronic Computers, 1960
- A SIGNED BINARY MULTIPLICATION TECHNIQUEThe Quarterly Journal of Mechanics and Applied Mathematics, 1951