Invited Paper: Enhanced Architectures, Design Methodologies and CAD Tools for Dynamic Reconfiguration of Xilinx FPGAs
Top Cited Papers
- 1 August 2006
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 1946147X,p. 1-6
- https://doi.org/10.1109/fpl.2006.311188
Abstract
The paper describes architectural enhancements to Xilinx FPGAs that provide better support for the creation of dynamically reconfigurable designs. These are augmented by a new design methodology that uses pre-routed IP cores for communication between static and dynamic modules and permits static designs to route through regions otherwise reserved for dynamic modules. A new CAD tool flow to automate the methodology is also presented. The new tools initially target the Virtex-II, Virtex-II Pro and Virtex-4 families and are derived from Xilinx's commercial CAD toolsKeywords
This publication has 11 references indexed in Scilit:
- Figaro - an automatic tool flowfor designs with dynamic reconfigurationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- The MOLEN polymorphic processorIEEE Transactions on Computers, 2004
- Dynamic reconfiguration for management of radiation-induced faults in FPGAsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2004
- An implementation of the Rijndael on Async-WASMIIPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2004
- Scalable Application-Dependent Network on Chip Adaptivity for Dynamical Reconfigurable Real-Time SystemsPublished by Springer Nature ,2004
- A lightweight approach for embedded reconfiguration of FPGAsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Dynamically inserting, operating, and eliminating thermal sensors of FPGA-based systemsIEEE Transactions on Components and Packaging Technologies, 2002
- A time-multiplexed FPGAPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Dynamic fault tolerance in FPGAs via partial reconfigurationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Reconfigurable computing systemsProceedings of the IEEE, 2002