Dynamic fault tolerance in FPGAs via partial reconfiguration
- 11 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 165-174
- https://doi.org/10.1109/fpga.2000.903403
Abstract
In this paper we present an on-line, multi- stage fault tolerant (FT) technique for applications mapped to partially and dynamically reconfigurable FPGAs. We show that partial reconfiguration enables unique FT features that cannot be achieved with conventional methods. Our tech- niques are integrated with the roving STARs approach to on- line fault detection and location (1). A STAR is a self-testing area of the FPGA where testing and diagnosis based on partial reconfiguration take place without any impact on the normal system operation. Roving the STARs across the FPGA tests the entire chip. Once faulty cells have been detected and located, we dynamically reconfigure slices of the FPGA so that the working area avoids the faulty cells. To increase fault tolerance, we also allow the reuse of defective cells whenever possible. We have successfully demonstrated a preliminary implementation on a 20X20 FPGA, where our approach detected, located, and tolerated a fault in a know defective FPGA.*Keywords
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