Operation of a novel negative differential conductance transistor fabricated in a strained Si quantum well
- 1 September 1997
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 18 (9) , 432-434
- https://doi.org/10.1109/55.622520
Abstract
The operation of a negative differential conductance (NDC) transistor fabricated on a high-mobility Si/Si/sub 1-x/Ge/sub x/ heterostructure wafer is described. The drain characteristic of this device shows a large NDC with current peak-to-valley ratios as high as 600 (100) at T=0.4 K (T=1.3 K). The NDC can be modulated over a wide range of current levels by either of two separately-contacted gate electrodes. The device shows bistable switching behaviour in both current- and voltage-controlled circuit configurations. The novel operating principle of this transistor is described, along with its potential for future logic and memory applications.Keywords
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