An experimental 4-Mbit CMOS EEPROM with a NAND-structured cell
- 1 October 1989
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 24 (5) , 1238-1243
- https://doi.org/10.1109/jssc.1989.572587
Abstract
No abstract availableKeywords
This publication has 11 references indexed in Scilit:
- A 16 Mb mask ROM with programmable redundancyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- An experimental 4 Mb CMOS EEPROM with a NAND structured cellPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A high density NAND EEPROM with block-page programming for microcomputer applicationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1989
- A 50-ns CMOS 256 K EEPROMIEEE Journal of Solid-State Circuits, 1988
- An in-system reprogrammable 32 K*8 CMOS flash memoryIEEE Journal of Solid-State Circuits, 1988
- A 256K CMOS EEPROM with enhanced reliability and testabilityPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1988
- A million-cycle CMOS 256 K EEPROMIEEE Journal of Solid-State Circuits, 1987
- A 128 K flash EEPROM using double-polysilicon technologyIEEE Journal of Solid-State Circuits, 1987
- A 256-kbit flash E/SUP 2/PROM using triple-polysilicon technologyIEEE Journal of Solid-State Circuits, 1987
- New ultra high density EPROM and flash EEPROM with NAND structure cellPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1987