Processing Enhanced SEU Tolerance in High Density SRAMs

1 December 1987

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Nuclear Science

Vol. 34 (6) , 1322-1325
https://doi.org/10.1109/tns.1987.4337473

Abstract

We report theoretical calculations and experimental verification of an increase in memory cell SEU tolerance when Sandia's 2μm-technology 16K SRAMs are fabricated with a radiation-hardened 1-μm CMOS process. An advanced 2D transient transport-plus-circuit simulator has been employed to calculate the differential contributions from each of the vertical dimensional changes in the transition from the 2-μm process to the 1-μm process. Error cross-section data, performed at the Berkeley cyclotron, on the first such device lot indicate that total improvement in threshold LET is a factor of 2 or better. A saturation phenomenon associated with the high-LET events is described and physical mechanisms responsible for the saturation are discussed.

Keywords

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