Identification of gate electrode discontinuities in submicron CMOS technologies, and effect on circuit performance

This publication has 6 references indexed in Scilit:

• Dual (n/sup +p/sup +/) polycide gate technology using Si-rich WSi/sub x/ to exterminate lateral dopant diffusion
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Anomalous Ti SALICIDE gate to source/drain shorts induced by dry Si etch during TiSi/sub 2/ local interconnect formation
  IEEE Electron Device Letters, 1994
• Use of electron-beam charging for in-process inspection of silicide complementary metal-oxide-semiconductor gate electrode isolation
  Applied Physics Letters, 1992
• Technology limitations for N/sup +//P/sup +/ polycide gate CMOS due to lateral dopant diffusion in silicide/polysilicon layers
  IEEE Electron Device Letters, 1991
• Comparison of transformation to low-resistivity phase and agglomeration of TiSi/sub 2/ and CoSi/sub 2/
  IEEE Transactions on Electron Devices, 1991
• Design of ion-implanted MOSFET's with very small physical dimensions
  IEEE Journal of Solid-State Circuits, 1974