An 84-mW 4-Gb/s clock and data recovery circuit for serial link applications
- 13 November 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A 4Gb/s serial link tracking clock and data recovery (CDR) circuit fabricated in 0.24 μm CMOS technology dissi- pates 84mW and occupies 0.3mm2. The input signal is 2× oversampled by 8 offset-cancelled receive amplifiers per receive clock cycle. The samples are processed by a phase controller to position the receive clocks at the center and the edge of the data eye using a semi-digital dual delay-locked loop (DLL) (3). The quiet-supply p-p jitter of the receive clock is 39ps with 0.33ps/mV supply sensitivity. It allows for plesio- chronous clocking with a frequency tolerance of ±400ppm. The worst case phase resolution is < 20ps.Keywords
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