A variable-frequency parallel I/O interface with adaptive power-supply regulation
- 1 November 2000
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 35 (11) , 1600-1610
- https://doi.org/10.1109/4.881205
Abstract
This paper presents a low-power high-speed CMOS signaling interface that operates off of an adaptively regulated supply. A feedback loop adjusts the supply voltage on a chain of inverters until the delay through the chain is equal to half of the input period. This voltage is then distributed to the I/O subsystem through an efficient switching power-supply regulator. Dynamically scaling the supply with respect to frequency leads to a simple and robust design consisting mostly of digital CMOS gates, while enabling maximum energy efficiency. The interface utilizes high-impedance drivers for operation across a wide range of voltages and frequencies, a dual-loop delay-locked loop for accurate timing recovery, and an input receiver whose bandwidth tracks with the I/O frequency to filter out high-frequency noise. Test chips fabricated in a 0.35-/spl mu/m CMOS technology achieve transfer rates of 0.2-1.0 Gb/s/pin with a regulated supply ranging from 1.3-3.2 V.Keywords
This publication has 13 references indexed in Scilit:
- A 2.6 GB/s multi-purpose chip-to-chip interfacePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 300 MIPS/W RISC core processor with variable supply-voltage scheme in variable threshold-voltage CMOSPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Adaptive bandwidth DLLs and PLLs using regulated supply CMOS buffersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 2.4 Gb/s/pin simultaneous bidirectional parallel link with per pin skew compensationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A dynamic voltage scaled microprocessor systemPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2000
- A fully digital, energy-efficient, adaptive power-supply regulatorIEEE Journal of Solid-State Circuits, 1999
- A 0.5-μm CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversamplingIEEE Journal of Solid-State Circuits, 1998
- A 700-Mb/s/pin CMOS signaling interface using current integrating receiversIEEE Journal of Solid-State Circuits, 1997
- A semidigital dual delay-locked loopIEEE Journal of Solid-State Circuits, 1997
- Precise delay generation using coupled oscillatorsIEEE Journal of Solid-State Circuits, 1993