Accurate analytical delay expressions for ECL and CML circuits and their applications to optimizing high-speed bipolar circuits
- 1 April 1990
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 25 (2) , 572-583
- https://doi.org/10.1109/4.52186
Abstract
No abstract availableThis publication has 18 references indexed in Scilit:
- Bipolar transistor scaling for minimum switching delay and energy dissipationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A propagation-delay expression and its application to the optimization of polysilicon emitter ECL processesIEEE Journal of Solid-State Circuits, 1988
- Self-aligned AlGaAs/GaAs HBT with low emitter resistance utilizing InGaAs cap layerIEEE Transactions on Electron Devices, 1988
- A 20-GHz frequency divider implemented with heterojunction bipolar transistorsIEEE Electron Device Letters, 1987
- AlGaAs/GaAs heterojunction bipolar transistors fabricated using a self-aligned dual-lift-off processIEEE Electron Device Letters, 1987
- High-speed frequency dividers using self-aligned AlGaAs/GaAs heterojunction bipolar transistorsIEEE Electron Device Letters, 1987
- Figure of merit for integrated bipolar transistorsSolid-State Electronics, 1986
- High-speed bipolar logic circuits with low power consumption for LSI-a comparisonIEEE Journal of Solid-State Circuits, 1982
- Heterostructure bipolar transistors and integrated circuitsProceedings of the IEEE, 1982
- A theory of transistor cutoff frequency (fT) falloff at high current densitiesIRE Transactions on Electron Devices, 1962