Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures
Top Cited Papers
- 7 February 2008
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems I: Regular Papers
- Vol. 55 (6) , 1441-1454
- https://doi.org/10.1109/tcsi.2008.917991
Abstract
The need for highly integrable and programmable analog-to-digital converters (ADCs) is pushing towards the use of dynamic regenerative comparators to maximize speed, power efficiency and reconfigurability. Comparator thermal noise is, however, a limiting factor for the achievable resolution of several ADC architectures with scaled supply voltages. While mismatch in these comparators can be compensated for by calibration, noise can irreparably hinder performance and is less straightforward to be accounted for at design time. This paper presents a method to estimate the input referred noise in fully dynamic regenerative comparators leveraging a reference architecture. A time-domain analysis is proposed that accounts for the time varying nature of the circuit exploiting some basic results from the solution of stochastic differential equations. The resulting symbolic expressions allow focusing designers' attention on the most influential noise contributors. Analysis results are validated by comparison with electrical simulations and measurement results from two ADC prototypes based on the reference comparator architecture, implemented in 0.18-mum and 90-nm CMOS technologies.Keywords
This publication has 14 references indexed in Scilit:
- A 65fJ/Conversion-Step 0-to-50MS/s 0-to-0.7mW 9b Charge-Sharing SAR ADC in 90nm Digital CMOSPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2007
- Efficient Calibration through Statistical Behavioral Modeling of a High-Speed Low-Power ADCPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2006
- A 10.6mW/0.8pJ power-scalable 1GS/s 4b ADC in 0.18/spl mu/m CMOS with 5.8GHz ERBWProceedings of the 39th conference on Design automation - DAC '02, 2006
- A 0.16pJ/Conversion-Step 2.5mW 1.25GS/s 4b ADC in a 90nm Digital CMOS ProcessPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2006
- Minimum achievable phase noise of RC oscillatorsIEEE Journal of Solid-State Circuits, 2005
- Yield and speed optimization of a latch-type voltage sense amplifierIEEE Journal of Solid-State Circuits, 2004
- CMOS Integrated Analog-to-Digital and Digital-to-Analog ConvertersPublished by Springer Nature ,2003
- Dynamic characterisation of high-speed latchingcomparatorsElectronics Letters, 2000
- Stochastic Differential EquationsPublished by Springer Nature ,1998
- Noise estimation in strobed comparatorsElectronics Letters, 1997