Full temperature single event upset characterization of two microprocessor technologies
- 1 January 1988
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Nuclear Science
- Vol. 35 (6) , 1619-1621
- https://doi.org/10.1109/23.25508
Abstract
No abstract availableThis publication has 4 references indexed in Scilit:
- Temperature and Epi Thickness Dependence of the Heavy Ion Induced Latchup Threshold for a CMOS/EPI 16K Static RAMIEEE Transactions on Nuclear Science, 1987
- Single Event Upset Dependence on Temperature or an NMOS/Resistive-Load Static RAMIEEE Transactions on Nuclear Science, 1986
- The Effect of Elevated Temperature on Latchup and Bit Errors in CMOS DevicesIEEE Transactions on Nuclear Science, 1986
- A Summary of JPL Single Event Upset Test Data from May 1982, Through January 1984IEEE Transactions on Nuclear Science, 1984