The Effect of Elevated Temperature on Latchup and Bit Errors in CMOS Devices
- 1 January 1986
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Nuclear Science
- Vol. 33 (6) , 1605-1609
- https://doi.org/10.1109/tns.1986.4334649
Abstract
Equipment for testing microcircuits at elevated temperatures for Single Event Phenomena (SEP) such as upset (SEU) and latchup (SEL) has been developed and measurements on several device types have been performed. Very large changes in cross-section and threshold LET have been observed over the temperature range of 25°C to 120°C for SEU and SEL.Keywords
This publication has 7 references indexed in Scilit:
- Single Event Upset Dependence on Temperature or an NMOS/Resistive-Load Static RAMIEEE Transactions on Nuclear Science, 1986
- Heavy Ion-Induced Single Event Upsets of Microcircuits; A Summary of the Aerospace Corporation Test DataIEEE Transactions on Nuclear Science, 1984
- Investigation of soft upsets in integrated circuit memories and charge collection in semiconductor test structures by the use of an ion microbeamNuclear Instruments and Methods in Physics Research, 1983
- Single Event Upset (SEU) of Semiconductor Devices - A Summary of JPL Test DataIEEE Transactions on Nuclear Science, 1983
- Error Analysis and Prevention of Cosmic Ion-Induced Soft Errors in Static CMOS RAMsIEEE Transactions on Nuclear Science, 1982
- Simulation of Cosmic-Ray Induced Soft Errors and Latchup in Integrated-Circuit Computer MemoriesIEEE Transactions on Nuclear Science, 1979
- High Temperature Schottky TTL LatchupIEEE Transactions on Nuclear Science, 1978