Fast-access BiCMOS SRAM architecture with a V/sub SS/ generator
- 1 April 1991
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 26 (4) , 513-517
- https://doi.org/10.1109/4.75048
Abstract
No abstract availableKeywords
This publication has 7 references indexed in Scilit:
- A 3.5 ns, 500 mW 16 kb BiCMOS ECL RAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Fast-access BiCMOS SRAM architecture with a VSS generatorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1990
- A 5 ns 1 Mb ECL BiCMOS SRAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1990
- SST-BiCMOS technology with 130 ps CMOS and 50 ps ECLPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1990
- BiCMOS circuit technology for a high-speed SRAMIEEE Journal of Solid-State Circuits, 1988
- A 7-ns/350-mW 64-kbit ECL-compatible RAMIEEE Journal of Solid-State Circuits, 1987
- 13-ns, 500-mW, 64-kbit ECL RAM using Hi-BiCMOS technologyIEEE Journal of Solid-State Circuits, 1986