13-ns, 500-mW, 64-kbit ECL RAM using Hi-BiCMOS technology
- 1 October 1986
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 21 (5) , 681-685
- https://doi.org/10.1109/jssc.1986.1052595
Abstract
No abstract availableKeywords
This publication has 7 references indexed in Scilit:
- A 12ns/350mW 16Kb ECL Compatible RAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1985
- 64Kb ECL RAM with redundancyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1985
- High speed BiCMOS VLSI technology with buried twin well structurePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1985
- A 25ns 64K SRAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1984
- A 28ns CMOS SRAM with bipolar sense amplifiersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1984
- A 20ns 64K CMOS SRAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1984
- A 16ns 16K bipolar RAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1983