Sub-60-nm quasi-planar FinFETs fabricated using a simplified process
- 1 October 2001
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 22 (10) , 487-489
- https://doi.org/10.1109/55.954920
Abstract
N-channel double-gate metal-oxide-semiconductor field-effect transistor (MOSFET) FinFETs with gate and fin dimensions as small as 30 nm have been fabricated using a new, simplified process. Short channel effects are effectively suppressed when the Si fin width is less than two-thirds of the gate length. The drive current for typical devices is found to be above 500 μA/μm (or 1 mA/μm, depending on the definition of the width of the double-gate device) for V/sub g/-V T =V/sub d/=1 V. The electrical gate oxide thickness in these devices is 21 /spl Aring/, determined from the first FinFET capacitance-versus-voltage characteristics obtained to date. These results indicate that the FinFET is a promising structure for the future manufacturing of integrated circuits with sub-60-nm feature size, and that double-gate MOSFETs can meet international technology roadmap for semiconductors performance specifications without aggressive scaling of the gate-oxide thickness.Keywords
This publication has 8 references indexed in Scilit:
- A folded-channel MOSFET for deep-sub-tenth micron eraPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Gate length scaling and threshold voltage control of double-gate MOSFETsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- MOSFET scaling into the 10 nm regimeSuperlattices and Microstructures, 2000
- Calixarene G-line double resist process with 15 nm resolution and large area exposure capabilityJournal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, 2000
- Ultrathin-body SOI MOSFET for deep-sub-tenth micron eraIEEE Electron Device Letters, 2000
- An analytical solution to a double-gate MOSFET with undoped bodyIEEE Electron Device Letters, 2000
- A computationally efficient model for inversion layer quantization effects in deep submicron N-channel MOSFETsIEEE Transactions on Electron Devices, 1996