A testable design of iterative logic arrays
- 1 November 1981
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems
- Vol. 28 (11) , 1037-1045
- https://doi.org/10.1109/tcs.1981.1084934
Abstract
No abstract availableKeywords
This publication has 7 references indexed in Scilit:
- A Functional Approach to Testing Bit-Sliced MicroprocessorsIEEE Transactions on Computers, 1981
- Fault Detection in Bilateral Arrays of Combinational CellsIEEE Transactions on Computers, 1978
- Truth-Table Verification of an Iterative Logic ArrayIEEE Transactions on Computers, 1976
- Multiple Fault Detection in Arrays of Combinational CellsIEEE Transactions on Computers, 1975
- Easily Testable Iterative SystemsIEEE Transactions on Computers, 1973
- Fault Detection in Iterative Logic ArraysIEEE Transactions on Computers, 1971
- Testing for faults in combinational cellular logic arraysPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1967