Leading-zero anticipatory logic for high-speed floating point addition
- 1 August 1996
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 31 (8) , 1157-1164
- https://doi.org/10.1109/4.508263
Abstract
This paper describes a new leading-zero anticipatory (LZA) logic for high-speed floating-point addition (FADD). This logic carries out the pre-decoding for normalization concurrently with addition for the significand. It also performs the shift operation of normalization in parallel with the rounding operation. The use of simple Boolean algebra allows the proposed logic to be constructed from a simple CMOS circuit. Its area penalty is as small as 30% of the conventional LZA method. The FADD core using the proposed logic was fabricated by 0.5 /spl mu/m CMOS technology with triple metal interconnections and runs at 164 MHz under the condition of V/sub DD/=3.3 V.Keywords
This publication has 16 references indexed in Scilit:
- A 40 MFLOPS 32-bit floating-point processorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A 50 MHz 24 b floating-point DSPPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A 1,000,000 transistor microprocessorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A 40 MHz 64-bit floating-point co-processorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A 0.4 μm 1.4 ns 32b dynamic adder using non-precharge multiplexers and reduced precharge voltage techniquePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 1.5-ns 32-b CMOS ALU in double pass-transistor logicIEEE Journal of Solid-State Circuits, 1993
- An 80-MFLOPS (peak) 64-b microprocessor for parallel computerIEEE Journal of Solid-State Circuits, 1992
- A 200-MHz 64-b dual-issue CMOS microprocessorIEEE Journal of Solid-State Circuits, 1992
- A 200-MFLOPS 100-MHz 64-b BiCMOS vector-pipelined processor (VPP) ULSIIEEE Journal of Solid-State Circuits, 1991
- Leading-zero anticipator (LZA) in the IBM RISC System/6000 floating-point execution unitIBM Journal of Research and Development, 1990