Power distribution synthesis for analog and mixed-signal ASICs in RAIL
- 30 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 17.4.1-17.4.5
- https://doi.org/10.1109/cicc.1993.590740
Abstract
The authors present new power distribution synthesis techniques that can handle realistic analog and mixed-signal performance concerns. The key ideas are to employ asymptotic waveform evaluation techniques to reduce complex macro, substrate, and package electrical models to accurate, low-order analytical expressions that can be quickly evaluated by a simulated annealing optimizer that selects and sizes the power bus topology while accommodating DC, AC, and transient constraints. RAIL, a new tool for power distribution, is used for this purpose. Experimental results demonstrate the importance of optimizing both topology selection and sizing, and the critical need to include transient as well as DC constraints during synthesis.Keywords
This publication has 14 references indexed in Scilit:
- Experimental results and modeling techniques for switching noise in mixed-signal integrated circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Simulation of substrate coupling in mixed-signal MOS circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Power and ground network topology optimization for cell based VLSIsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Rapid simulation of substrate coupling effects in mixed-mode ICsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Low noise digital logic techniquesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A dynamic programming approach to the power supply net sizing problemPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- System-level routing of mixed-signal ASICs in WRENPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1992
- Asymptotic waveform evaluation for timing analysisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1990
- Hierarchical VLSI Routing--An Approximate Routing ProcedureIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1985
- Computation of Power Supply Nets in VLSI LayoutPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1981