Three-dimensional effects in dynamically triggered CMOS latchup
- 1 September 1989
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 36 (9) , 1683-1690
- https://doi.org/10.1109/16.34230
Abstract
An analysis of three-dimensional (3-D) effects in CMOS latchup under dynamic conditions that expands on previous work limited to steady state is presented. Measurements of the minimum duration of voltage pulses and the ramp slew rate needed to induce latchup and have been performed on devices of different widths and layouts, and the latchup susceptibility to transient stimuli has been found to depend on the device dimensions and geometry. By means of simple analytical models it is shown that such a dependence originates from the nonideal scaling of the distributed resistances and capacitances due to the 3-D nature of the structure terminating regionKeywords
This publication has 5 references indexed in Scilit:
- Hysteresis cycle in the latch-up characteristic of wide CMOS structuresIEEE Electron Device Letters, 1988
- Three-dimensional distribution of CMOS latch-up currentIEEE Electron Device Letters, 1987
- Three-dimensional effects in CMOS latch-upPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1986
- Latchup in CMOS TechnologyPublished by Springer Nature ,1986
- Layout and bias considerations for preventing transiently triggered latchup in CMOSIEEE Transactions on Electron Devices, 1984