Analytical modeling of the substrate effect on accumulation-mode SOI pMOSFETs at room temperature and at 77 K
- 30 June 1997
- journal article
- Published by Elsevier in Microelectronic Engineering
- Vol. 36 (1-4) , 375-378
- https://doi.org/10.1016/s0167-9317(97)00083-x
Abstract
No abstract availableKeywords
This publication has 4 references indexed in Scilit:
- An analytical back-gate bias effect model for ultrathin SOI CMOS devicesIEEE Transactions on Electron Devices, 1993
- An analytical model for back-gate effects on ultrathin-film SOI MOSFET'sIEEE Electron Device Letters, 1991
- Model for the potential drop in the silicon substrate for thin-film SOI MOSFETsElectronics Letters, 1990
- MOS device modeling at 77 KIEEE Transactions on Electron Devices, 1989