Analysis and modeling of MOS devices with gate oxide short failures
- 1 January 1991
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 2164-2167 vol.4
- https://doi.org/10.1109/iscas.1991.176718
Abstract
A circuit level model for failures causing shorts in the oxide of the gate electrode (GOS) is presented. Experimental results show that the influence of the width of a short between gate and channel in a MOS device is low in comparison with the location in the length direction. The model takes advantage of this result. A unidimensional (length) model for GOS faults is proposed. The experimental results have been obtained by measuring devices with faults where the failures have been introduced by design. The model reduces the complexity of electrical simulations (in comparison with previous unidimensional models) when parametric deviations on an assumed GOS-faulty circuit are analyzed. Results verifying the adequacy of the models and comparison with other research data are presented, considering the effect of the failure on the input and output characteristics of the devices.<>Keywords
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