110-GB/s simultaneous bidirectional transceiver logic synchronized with a system clock
- 1 January 1999
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 34 (11) , 1526-1533
- https://doi.org/10.1109/4.799856
Abstract
No abstract availableKeywords
This publication has 8 references indexed in Scilit:
- Storage hierarchy to support a 600 MHz G5 S/390 microprocessorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A 1860 kG CMOS gate array with GTL input flip-flop circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Simultaneous bidirectional signalling for IC systemsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Simultaneous bidirectional transceiver logicIEEE Micro, 1999
- Spider: a high-speed network interconnectIEEE Micro, 1997
- A CMOS gate array with 600 Mb/s simultaneous bidirectional I/O circuitsIEEE Journal of Solid-State Circuits, 1995
- A 900 Mb/s bidirectional signaling schemeIEEE Journal of Solid-State Circuits, 1995
- Automatic impedance controlPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1993