Interconnect estimation and planning for deep submicron designs
- 20 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 10 references indexed in Scilit:
- Optimal wiresizing under the distributed Elmore delay modelPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Interconnect delay estimation models for synthesis and design planningPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1999
- A stochastic wire-length distribution for gigascale integration (GSI). II. Applications to clock frequency, power dissipation, and chip size estimationIEEE Transactions on Electron Devices, 1998
- Is interconnect the weak link?IEEE Circuits and Devices Magazine, 1998
- The test of time. Clock-cycle estimation and test challenges for future microprocessorsIEEE Circuits and Devices Magazine, 1998
- Planning for performancePublished by Association for Computing Machinery (ACM) ,1998
- Analysis and justification of a simple, practical 2 1/2-D capacitance extraction methodologyPublished by Association for Computing Machinery (ACM) ,1997
- Interconnect design for deep submicron ICsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1997
- Global interconnect sizing and spacing with consideration of coupling capacitancePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1997
- The Transient Response of Damped Linear Networks with Particular Regard to Wideband AmplifiersJournal of Applied Physics, 1948