Measurement of plasma etch damage by a new slow trap profiling technique

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Abstract
MOS capacitor structures with plasma damaged oxides have been used to demonstrate a new technique for profiling slow traps at the Si-SiO/sub 2/ interface. The technique measures the density and trapping rate of slow traps by stepping the gate voltage in small increments and monitoring the resulting substrate current transients, thereby producing a profile of the traps in energy and response time. The response time is a function of the trap's energy position and distance from the interface. Some traps created by plasma etching are not obvious in quasistatic CV measurements, yet are clearly evident when the new technique is used. Results show an increase in slow trap densities and response times in the upper half of the silicon bandgap with long plasma overetch times. In comparison, wet etched control devices show only low densities of slow traps with shorter response times around the midgap.