Magic's Circuit Extractor

1 January 1986

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Design & Test of Computers

Vol. 3 (1) , 24-34
https://doi.org/10.1109/mdt.1986.294914

Abstract

This fast hierarchical circuit extractor for the Magic VLSI layout system derives its speed from its ability to handle hiearchical arrays, and from a new algorithm based on corner-stitching, a geometrical data structure for representing Manhattan shapes. Corner-stitching's ability to find adjacent mask information is critical to the basic extractor speed, and its ability to search areas makes the hiearchical extraction algorithm practical. The extractor is incremental, necessitating re-extraction of only a few cells after a layout is modified. It accepts a hierarchical layout that may contain nearly arbitrary overlaps between cells, and produces a circuit description with the same hierarchical structure as the layout. The extractor can completely extract a 37,000-transistor chip in 20 minutes of VAX CPU time, or incremetally in an average of 8 minutes. The extractor processes 50-65 FETS per second on a VAX-11/780 running Unix. if only substrate capacitance is being extracted. If coupling capacitance is also extracted, the basic extractor processes 25-35 transistors per second.

Keywords

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