On numerical weight optimization for random testing
- 30 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 223-230
- https://doi.org/10.1109/edac.1993.386472
Abstract
The author points out that to make pseudorandom testing usable for circuits containing random pattern resistant faults, input probabilities are weighted. New results on numerical weight optimization are presented. First, two cost functions which are aimed at minimizing the expected test length and at maximizing the expected fault coverage, respectively, are derived. Optimizations based on precomputed tests are then considered. Applying numerical methods to such optimizations yields a method which improves existing strategies.Keywords
This publication has 11 references indexed in Scilit:
- The random testability of the n-input AND gatePublished by Springer Nature ,2005
- 3-Weight Pseudo-Random Test Generation Based on a Deterministic Test SetPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Advanced automatic test pattern generation and redundancy identification techniquesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Built-in self-test with weighted random pattern hardwarePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A new procedure for weighted random built-in self-testPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- On computing signal probability and detection probability of stuck-at faultsIEEE Transactions on Computers, 1990
- Testability-Driven Random Test-Pattern GenerationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- On computing optimized input probabilities for random testsPublished by Association for Computing Machinery (ACM) ,1987
- PROTEST: A Tool for Probabilistic Testability AnalysisPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1985
- STAFAN: An Alternative to Fault SimulationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1984