NiSi salicide technology for scaled CMOS

This publication has 13 references indexed in Scilit:

• A NiSi salicide technology for advanced logic devices
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Nitrogen-doped nickel monosilicide technique for deep submicron CMOS salicide
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• CMOS device scaling beyond 100 nm
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• 30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Deep sub-100 nm CMOS with ultra low gate sheet resistance by NiSi
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Self-aligned nickel-mono-silicide technology for high-speed deep submicrometer logic CMOS ULSI
  IEEE Transactions on Electron Devices, 1995
• Sub-20 ps high-speed ECL bipolar transistor with low parasitic architecture
  IEEE Transactions on Electron Devices, 1995
• Analysis of resistance behavior in Ti- and Ni-salicided polysilicon films
  IEEE Transactions on Electron Devices, 1994
• A new contact plug technique for deep-submicrometer ULSI is employing selective nickel silcidation of polysilicon with a titanium nitride stopper
  IEEE Transactions on Electron Devices, 1993
• Analysis of Anomalously Large Junction Leakage Current of Nickel Silicided N-Type Diffused Layer and Its Improvement
  Published by Japan Society of Applied Physics ,1993