Advantages of heterogeneous logic block architecture for FPGAs
- 30 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 7.4.1-7.4.5
- https://doi.org/10.1109/cicc.1993.590578
Abstract
The authors consider field programmable gate arrays (FPGAs) that use two different sizes of lookup table (LUT) logic blocks and investigate the area-efficiency of different mixtures of different sizes of LUTs. Experimental results on a set of benchmark circuits indicate that several heterogeneous architectures achieve significant reduction in the number of programming bits and logic block pins compared to the industry standard 4-input LUTs. A 6-LUT/4-LUT combination will likely exhibit better performance with nearly equivalent area than a homogeneous 4-LUT FPGA.Keywords
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