A 2.5-ns, 40-mW, 4×4 GaAs multiplier in two's complement mode

Publisher Website

1 June 1987

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits

Vol. 22 (3) , 409-414
https://doi.org/10.1109/jssc.1987.1052740

Abstract

No abstract available

Keywords

This publication has 5 references indexed in Scilit:

Packaged 7 mW, 1.2 GHz dynamic 60/61 GaAs prescaler
Electronics Letters, 1986
A GaAs 16x16 bit parallel multiplier
IEEE Journal of Solid-State Circuits, 1983
A high-speed LSI GaAs 8x8 bit parallel multiplier
IEEE Journal of Solid-State Circuits, 1982
High-Speed Arithmetic in Binary Computers
Proceedings of the IRE, 1961
A SIGNED BINARY MULTIPLICATION TECHNIQUE
The Quarterly Journal of Mechanics and Applied Mathematics, 1951