On the evaluation of process-fault tolerance ability of CMOS integrated circuits

Publisher Website

4 December 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

https://doi.org/10.1109/test.1990.114115

Abstract

No abstract available

Keywords

This publication has 7 references indexed in Scilit:

A CMOS fault extractor for inductive fault analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988
Optimal layout to avoid CMOS stuck-open faults
Published by Association for Computing Machinery (ACM) ,1987
VLASIC: A Catastrophic Fault Yield Simulator for Integrated Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1986
Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1985
Inductive Fault Analysis of MOS Integrated Circuits
IEEE Design & Test of Computers, 1985
Modeling of defects in integrated circuit photolithographic patterns
IBM Journal of Research and Development, 1984
Yield Model for Productivity Optimization of VLSI Memory Chips with Redundancy and Partially Good Product
IBM Journal of Research and Development, 1980