Simultaneous power supply, threshold voltage, and transistor size optimization for low-power operation of CMOS circuits
- 1 December 1998
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Vol. 6 (4) , 538-545
- https://doi.org/10.1109/92.736125
Abstract
This paper demonstrates a new approach for minimizing the total of the static and the dynamic power dissipation components in a complementary metal-oxide-semiconductor (CMOS) logic network required to operate at a specified clock frequency. The algorithms presented can be used to design ultralow-power CMOS logic circuits by joint optimization of supply voltage, threshold voltage and device widths. The static, dynamic and short-circuit energy components are considered and an efficient heuristic is developed that delivers over an order of magnitude savings in power over conventional optimization methods.Keywords
This publication has 10 references indexed in Scilit:
- Device-circuit Optimization For Minimal Energy And Power Consumption In Cmos Random Logic NetworksPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Circuit techniques for low power CMOS GSIPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Optimal low power interconnect networksPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 200 mV self-testing encoder/decoder using Stanford ultra-low-power CMOSPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Minimizing power consumption in digital CMOS circuitsProceedings of the IEEE, 1995
- An exact solution to the transistor sizing problem for CMOS circuits using convex optimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1993
- Trading speed for low power by choice of supply and threshold voltagesIEEE Journal of Solid-State Circuits, 1993
- Incremental techniques for the identification of statically sensitizable critical pathsPublished by Association for Computing Machinery (ACM) ,1991
- Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulasIEEE Journal of Solid-State Circuits, 1990
- CMOS Circuit Speed and Buffer OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987