An investigation on parasitic couplings and feedback loops in the CMOS circuits
- 13 January 2003
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 4 references indexed in Scilit:
- On network partitioning algorithm of large-scale CMOS circuitsIEEE Transactions on Circuits and Systems, 1989
- Network Partitioning and Ordering for MOS VLSI CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- A Survey of Switch-Level AlgorithmsIEEE Design & Test of Computers, 1987
- Depth-First Search and Linear Graph AlgorithmsSIAM Journal on Computing, 1972