Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration
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- 7 August 2002
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 37 (2) , 183-190
- https://doi.org/10.1109/4.982424
Abstract
A model describing the maximum clock frequency (FMAX) distribution of a microprocessor is derived and compared with wafer sort data for a recent 0.25-/spl mu/m microprocessor. The model agrees closely with measured data in mean, variance, and shape. Results demonstrate that within-die fluctuations primarily impact the FMAX mean and die-to-die fluctuations determine the majority of the FMAX variance. Employing rigorously derived device and circuit models, the impact of die-to-die and within-die parameter fluctuations on future FMAX distributions is forecast for the 180, 130, 100, 70, and 50-nm technology generations. Model predictions reveal that systematic within-die fluctuations impose the largest performance degradation resulting from parameter fluctuations. Assuming a 3/spl sigma/ channel length deviation of 20%, projections for the 50-nm technology generation indicate that essentially a generation of performance gain can be lost due to systematic within-die fluctuations. Key insights from this work elucidate the recommendations that manufacturing process controls be targeted specifically toward sources of systematic within-die fluctuations, and the development of new circuit design methodologies be aimed at suppressing the effect of within-die parameter fluctuations.Keywords
This publication has 13 references indexed in Scilit:
- Intra-field gate CD variability and its impact on circuit performancePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A circuit-level perspective of the optimum gate oxide thicknessIEEE Transactions on Electron Devices, 2001
- A minimum total power methodology for projecting limits on CMOS GSIIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2000
- The electronic structure at the atomic scale of ultrathin gate oxidesNature, 1999
- Technology and design challenges for low power and high performancePublished by Association for Computing Machinery (ACM) ,1999
- A physical alpha-power law MOSFET modelIEEE Journal of Solid-State Circuits, 1999
- High-performance microprocessor designIEEE Journal of Solid-State Circuits, 1998
- Low power microelectronics: retrospect and prospectProceedings of the IEEE, 1995
- Delay analysis of series-connected MOSFET circuitsIEEE Journal of Solid-State Circuits, 1991