Noise computation in single chip packages
- 1 May 1996
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part B
- Vol. 19 (2) , 350-360
- https://doi.org/10.1109/96.496039
Abstract
No abstract availableKeywords
This publication has 11 references indexed in Scilit:
- CBGA vs. CQFP: electrical performance comparison and tradeoff studyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Delay factors for mainframe computersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Modeling and simulation of switching noise with the associated package resonance for high speed digital circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Resonance analysis and simulation in packagesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Effect of CMOS driver loading conditions on simultaneous switching noiseIEEE Transactions on Components, Packaging, and Manufacturing Technology: Part B, 1994
- An investigation of delta-I noise on integrated circuitsIEEE Transactions on Electromagnetic Compatibility, 1993
- Inductance and resistance computations for three-dimensional multiconductor interconnection structuresIEEE Transactions on Microwave Theory and Techniques, 1992
- Simultaneous switching ground noise calculation for packaged CMOS devicesIEEE Journal of Solid-State Circuits, 1991
- Delta-I noise specification for a high-performance computing machineProceedings of the IEEE, 1985
- Three-Dimensional Inductance Computations with Partial Element Equivalent CircuitsIBM Journal of Research and Development, 1979