High-performance and low-power challenges for sub-70 nm microprocessor circuits
- 25 June 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 5 references indexed in Scilit:
- A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnectsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Dual-threshold voltage assignment with transistor sizing for low power CMOS circuitsIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2001
- Interconnect limits on gigascale integration (GSI) in the 21st centuryProceedings of the IEEE, 2001
- A completey on-chip voltage regulation technique for low power digital circuitsPublished by Association for Computing Machinery (ACM) ,1999
- Dual Threshold Voltages And Substrate Bias: Keys To High Performance, Low Power, 0.1 /spl mu/m Logic DesignsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1997