Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits
- 1 April 2001
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Vol. 9 (2) , 390-394
- https://doi.org/10.1109/92.924061
Abstract
We demonstrate a novel algorithm for assigning the threshold voltage to the gates in a digital random logic complementary metal-oxide-semiconductor (CMOS) circuit for a dual-threshold voltage process. The tradeoff between static and dynamic power consumption has been explored. When used along with device sizing and supply voltage reduction techniques for low power, the proposed algorithm can reduce the total power dissipation of a circuit by as much as 50%.Keywords
This publication has 12 references indexed in Scilit:
- A 200 mV self-testing encoder/decoder using Stanford ultra-low-power CMOSPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Low threshold voltage quarter micron MOSFETs for low power applicationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Simultaneous power supply, threshold voltage, and transistor size optimization for low-power operation of CMOS circuitsIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1998
- Design and optimization of low voltage high performance dual threshold CMOS circuitsPublished by Association for Computing Machinery (ACM) ,1998
- Supply and threshold voltage scaling for low power CMOSIEEE Journal of Solid-State Circuits, 1997
- Simultaneous driver and wire sizing for performance and power optimizationIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1994
- An exact solution to the transistor sizing problem for CMOS circuits using convex optimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1993
- Trading speed for low power by choice of supply and threshold voltagesIEEE Journal of Solid-State Circuits, 1993
- Optimization of high-speed CMOS logic circuits with analytical models for signal delay, chip area, and dynamic power dissipationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1990
- CMOS Circuit Speed and Buffer OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987