Unified methodology for resolving power-performance tradeoffs at the microarchitectural and circuit levels
- 1 January 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 166-171
- https://doi.org/10.1109/lpe.2002.146731
Abstract
Evaluation of architectural tradeoffs is complicated by implications in the circuit domain which are typically not captured in the analysis but substantially affect the results. We propose a metric of hardware intensity (/spl eta/), which is useful for evaluating issues that affect both circuits and architecture. Analyzing data for actual designs we show how to measure the introduced parameters and discuss variations between observed results and common theoretical assumptions. For a power-efficient design we derive relations for /spl eta/ and supply voltage V under progressively more general situations, and incorporate /spl eta/ into a prior art architectural energy-efficiency criterion. Then, a more general relation is derived for the optimal balance between the architectural complexity, hardware intensity and power supply. Modified forms for these relations are obtained in special cases where the supply voltage is constrained or when clock gating is disallowed.Keywords
This publication has 9 references indexed in Scilit:
- Clocking strategies and scannable latches for low power applicationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Energy-delay efficiency of VLSI computationsPublished by Association for Computing Machinery (ACM) ,2002
- Unified architecture level energy-efficiency metricPublished by Association for Computing Machinery (ACM) ,2002
- Low-power CMOS with subvolt supply voltagesIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2001
- Optimization of high-performance superscalar architectures for energy efficiencyPublished by Association for Computing Machinery (ACM) ,2000
- Energy dissipation in general purpose microprocessorsIEEE Journal of Solid-State Circuits, 1996
- Energy efficient CMOS microprocessor designPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1995
- Low-power CMOS digital designIEEE Journal of Solid-State Circuits, 1992
- Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuitsIEEE Journal of Solid-State Circuits, 1984